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PI6C103
Precision Clock Synthesizer for Mobile PCs
Features
Two copies of CPU clock 100 MHz or 66.6 MHz operation Six copies of PCI clock, (synchronous with CPU clock) Two copies of REF clock @ 14.31818 MHz One copy of 48 MHz One copy of selectable 48/24 MHz Power management control input pins Isolated core VDD, VSS pins for noise reduction 28-pin SSOP (H) and TSSOP (L) packages 66 MHz 0.67% 1.35% 1.79% 100 MHz 0.65% 1.35% 1.79%
Description
The PI6C103 is a high-speed, low-noise clock generator designed to work with the PI6C18X clock buffer to meet all clock needs for Mobile Intel Architecture platforms. System clock frequencies of 66.6 MHz and 100 MHz are supported. Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers everything except the CPU clock. The 2.5V power supply is used to power the CPUCLK outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PWR_DWN# signal may be used to orderly power down (or up) the system. CPU and PCI clocks may also be stopped by the CPU_STOP# and PCI_STOP# signals. The PI6C103 contains the Spread Spectrum function for only those clocks that synchronize to the CPU clocks (CPU and PCI clocks).
SSC Options: Device PI6C103 PI6C103-05 PI6C103-06
Block Diagram
XTAL_IN XTAL_OUT REF OSC 2
Pin Configuration
REF [0:1]
VSS XTAL_IN XTAL_OUT PCICLK_F PCICLK1 PCICLK2 VSS VDD PCICLK3 PCICLK4 PCICLK5 VDD 48 MHz 48-24MHz/TS#
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD REF1/SEL48# REF0/Spread# VDD2 CPUCLK0 CPUCLK1 VSS2 VSS PCI_STOP# VDD CPU_STOP# PWR_DWN# SEL100/66# VSS
SPREAD# SEL100/66# PLL1 DIV CPU_STOP#
2
CPUCLK [0:1] PCICLK [1:5] PCICLK_F
5 PCI_STOP#
28-Pin H, L
PWR_DWN# TS# 48 MHz PLL2 /2 SEL48# MUX 48/24 MHz
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PI6C103 Precision Clock Synthesizer for Mobile PCs
Pin Description
28-Pin Pack age Pin 2 3 4 5,6,9,10,11 13 14 16 17 18 20 23,24 26 Qty. 1 1 1 5 1 1 1 1 1 1 2 1 Type Input O utput O utput O utput O utput Symbol XTAL_IN XTAL_O UT PCICLK _F 14.318 MHz crystal input 14.318 MHz crystal output 3.3V free running PCI clock output D e s cription
PCICLK [1- 5] 3.3V PCI Clock outputs 48MHz 3.3V 48MHz clock output 3.3V 48 or 24MHz output and Hi- Z state strapping option(2,5) Strap Low = Enter Hi- Z state mode for testing, Strap High = N ormal operation Select for enabling 100 MHz or 66 MHz CPU clock(5) H = 100 MHz, L = 66 MHz Device enters power down mode when LO W5 When Low, stop CPU clocks in LO W state When signal LO W, stops all PCI clocks in LO W state except for PCICLK _F output(5)
O utput 48- 24MHz/TS# Input Input Input Input O utput O utput SEL100/66# PWR_DWN # CPU_STO P# PCI_STO P#
CPUCLK [1- 0] 2.5V CPU clock outputs 3.3V 14.318 MHz reference clock output and power- on spread spectrum enable strap option(3,5) REF0/Spread# Strap Low = Spread spectrum clocking enable Strap High = Spread spectrum clocking disable 3.3V 14.318 MHz reference clock output and power- on 48/24 MHz select strap option4,5 REF1/SEL48# Pin 14 output = 48 MHz when straped LO W Pin 14 output = 24 MHz when strapped HIGH VDD VS S VDD2 VSS2 3.3V Power 3.3V Ground 2.5V Power 2.5V Ground
27 8,12,19,28 1,7,15,21 25 22
Notes:
1 1
O utput Power Power
1 1
Power Power
1. VDD and VSS names in the above table reflect a likely internal power and ground partition to reduce the effects of internal noise on the performance of the device. In reality, the platform will be configured with the same voltage VDD pins tied to a common supply and all VSS pins being common. The VDD/VSS naming convention above is done to show how the pinout is dominated by the need to isolate all the signals. 2. The output frequency at this pin is dependent on the power on strapping option at pin 27. A 48 MHz output when power-on strapped LOW, and 24 MHz output when strapped HIGH. This pin also serves as Hi-Z state strapping option during power-on configuration. During power-on, the PI6C103 will sample the value at this pin. Strapped LOW for Hi-Z state mode and HIGH for normal operation. 3. This is a dual function pin. During power-on, all clock outputs are disabled, and the PI6C103 will sample the spread spectrum enable/disable strapping option. After the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become a 14.318 MHz reference clock output. The Power-on latency needs to be less than 3ms after the supply voltage stabilized. 4. This is a dual function pin. During power-on, all clocks are disabled, and PI6C103 will sample the SEL48# strapping option. After the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become another 14.318 MHz reference clock output. The poweron latency needs to be less than 3ms after the supply voltage stabilized. 5. Internally pulled up with resistor min.value of 50k.
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PI6C103 Precision Clock Synthesizer for Mobile PCs
Select Functions
SEL100/66# 0 1 CPUCLK[0:1] 66 MHz 100 MHz
Function Description
TS# 0 1 Function D e s cription Hi- Z Normal Outputs CPU Hi- Z 100/66 MHz PCI, PCI_ F Hi- Z 33 MHz REF Hi- Z 14.318 MHz 48/24M Hi- Z 48/24 MHz 48M Hi- Z 48 MHz
Clock Enable Configuration
CPU_STOP# X 0 0 1 1 PCI_STOP# X 0 1 0 1 PWR_D WN# 0 1 1 1 1 CPUCLK [0:1] low low low 100/66 MHz 100/66 MHz PCICLK PCICLK_F [1:5] low low 33 MHz low 33 MHz low 33 MHz 33 MHz 33 MHz 33 MHz Othe r Clocks stopped running running running running Crys tal off running running running running VCO's off running running running running 48M Hz off running running running running
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PI6C103 Precision Clock Synthesizer for Mobile PCs
Power Management Timing
Signal CPU_STOP# Signal State 0 (disabled) 1 (enabled) PCI_STOP# 0 (disabled) 1 (enabled) PWR_DWN# 1 (normal operation) 0 (power down) Late ncy No. of ris ing e dge s of fre e running PCICLK 1 1 1 1 3ms 2 max.
Notes: 1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between when the clock disable goes low/high to when the first valid clock comes out of the device. 2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid clocks are driven from the device. CPU_STOP# is an input signal used to turn off the CPU clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock and is internally synchronized to the external PCICLK_Foutput. All other clocks continue to run while the CPU clocks are disabled. The CPU clocks are always stopped in a low state and started guaranteeing that the high pulse width is a full pulse. CPU clock on latency is 2 or 3 CPU clocks and CPU clock off latency is 2 or 3 CPU clocks.
CPUCLK
(Internal) (Internal)
CPUCLK
(Free-running)
PCICLK_F
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK
(External)
CPU_STOP# Timing Diagram
Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F. 4. ON/OFF latency shown in the diagram is 2 CPU clocks. 5. All other clocks continue to run undisturbed. 6. PWR_DWN# , PCI_STOP# are shown in a high state. 7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz. 225
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PI6C103 Precision Clock Synthesizer for Mobile PCs
PCI_STOP# is an input signal used to turn off PCI clocks for low power operation. PCI clocks are stopped in the low state and started
CPUCLK
(Internal) (Internal)
with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic.
PCICLK
(Free-running)
PCICLK_F
CPU_STOP# PCI_STOP# PWR_DWN#
(External)
PCICLK
Notes: 1. All timing is referenced to the CPUCLK. 2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output. 3 Internal means inside the chip. 4. All other clocks continiue to run undisturbed. 5. PWR_DWN# CPU_STOP# are shown in a high state. 6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
PCI_STOP# Timing Diagram
The PWR_DWN# is used to place the device in a very low power state. PWR_DWN# is an asynchronous active low input. Internal clocks are stopped after the device is put in power-down mode.
CPUCLK
(Internal) (Internal)
The power-on latency is less than 3ms. PCI_STOP# and CPU_STOP# are dont cares during the power-down operations. The REF clock is stopped in the LOW state as soon as possible.
PCICLK
PWR_DWN# CPUCLK
(External)
(External)
PCICLK
VCO Crystal
Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part. 4. The Shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown wth respect to 66 MHz. Similar operations as CPU = 100 MHz.
PWR_DWN# Timing Diagram
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PI6C103 Precision Clock Synthesizer for Mobile PCs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................ 65C to +150C Ambient Temperature with Power Applied ............................. 0C to +70C 3.3V Supply Voltage to Ground Potential ............................. 0.5V to +4.6V 2.5V Supply Voltage to Ground Potential ............................. 0.5V to +3.6V DC Input Voltage ................................................................... 0.5V to +4.6V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
(VDDQ3 = +3.3V 5%, VDDQ2 = +2.5V 5%, TA = 0C to +70C)
PI6C102-16 Condition Powerdown Mode (PWRDWN# =0) Active 66 MHz SEL 100/66# = 0 Active 100 MHz SEL 100/66# = 1
M ax. 2.5V Supply Cons umption M ax. dis cre te cap loads , VDDQ2 = 2.625V All s tatic inputs = VDDQ3 or VSS 100A 72mA 100mA
M ax. 3.3V Supply Cons umption M ax. dis cre te cap loads , VDDQ3 = 3.465V All s tatic inputs = VDDQ3 or VSS 500A 170mA 170mA
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PI6C103 Precision Clock Synthesizer for Mobile PCs
DC Operating Specifications
Symbol VDD = 3.3V 5% VIH VIL IIL VDD = 2.5V 5% VOH VOL VDD = 3.3V 5% VOH VOL VDD = 3.3V 5% VPOH VPOL PCI Bus output high voltage PCI Bus output low voltage IOH = - 1mA IOL = 1mA 2.4 0.55 V Output high voltage Output low voltage IOH = - 1mA IOL = 1mA 2.0 0.4 V Output high voltage Output low voltage IOH = - 1mA IOL = 1mA 2.0 0.4 V Input high voltage Input low voltage Input leakage current 0 < VIN < VDD VDD 2.0 VSS - 0.3 -5 VDD +0.3 0.8 +5 V Parame te rs Conditions M in. M ax. Units
CIN CXTAL COUT LPIN TA
Input pin capacitance Xtal pins capacitance Output pin capacitance Pin Inductance Ambient Temperature No airflow 0 13.0
5 22.5 6 7 70 nH C pF
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PI6C103 Precision Clock Synthesizer for Mobile PCs
Buffer Specifications
Buffe r Name CPU REF, 48/24 MHz PCI/REF VDD Range (V) 2.375 - 2.625 3.135 - 3.465 3.135 - 3.465 Impe dance (W) 6.8 ~ 17.3 20 - 60 12 - 55 Buffe r Type Type 1 Type 3 Type 5
Type 1: CPU Clock Buffers (2.5V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 2.5V Type 1 output rise edge rate 2.5V Type 1 output fall edge rate Conditions VOUT = 1.0V VOUT = 2.375V VOUT = 1.2V VOUT = 0.3V 2.5V 5% @ 0.4V- 2.0V 2.5V 5% @ 2.0V- 0.4V 1 1 81 60 4 4 V/ns M in. - 78 - 67 mA Typ. M ax. Units
Type 3: REF Buffers (3.3V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 3 output rise edge rate 3.3V Type 3 output fall edge rate Conditions VOUT = 1.0V VOUT = 2.375V VOUT = 1.2V VOUT = 0.3V 3.3V 5% @ 0.4V- 2.4V 3.3V 5% @ 2.4V- 0.4V 0.5 0.5 29 27 2 2 V/ns M in. - 29 - 23 mA Typ. M ax. Units
Type 5: PCI Clock Buffers (3.3V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 5 output rise edge rate 3.3V Type 5 output fall edge rate Conditions VOUT = 1.0V VOUT = 3.135V VOUT = 1.95V VOUT = 0.4V 3.3V 5% @ 0.4V- 2.4V 3.3V 5% @ 2.4V- 0.4V 1 1 30 38 4 4 V/ns M in. - 33 - 33 mA Typ. M ax. Units
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PI6C103 Precision Clock Synthesizer for Mobile PCs
AC Timing
Figure 1. Hos t Clock to PCI CLK Offs e t tHKP (2.5V) tHKH (2.5V) tHKL (2.5V) tHRISE (2.5V) tHFALL (2.5V) tJITTER (2.5V) Duty Cycle (2.5V) tHSKW (2.5V) tPZL, tPZH tPLZ, tPHZ tHSTB tPKP tPKPS tPKH tPKL tPSKW tHPOFFSET tPSTB Parame te rs Host CLK period Host CLK high time Host CLK low time Host CLK rise time Host CLK fall time Host CLK Jitter Measured at 1.25V Host Bus CLK Skew Output enable delay Output disable delay Host CLK Stabilization from power- up PCI CLK period PCI CLK period stability PCI CLK high time PCI CLK low time PCI Bus CLK Skew Host to PCI Clock Offset PCI CLK Stabilization from power- up 1.5 12.0 12.0 500 4.0 3 1.5 30.0 1.0 1.0 45 66 M Hz M in. 15.0 5.2 5.0 0.4 0.4 1.6 1.6 250 55 175 8.0 8.0 3 500 12.0 12.0 500 4.0 3 30.0 1.0 1.0 45 M ax. 15.5 100 M Hz M in. 10.0 3.0 2.8 0.4 0.4 1.6 1.6 250 55 175 8.0 8.0 3 500 ps % ps ns ms ns ps ns ps ns ms ns M ax. 10.5 Units
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2.5V 1.25V Host CLK t 1.25V V
HSKW SS
PI6C103 Precision Clock Synthesizer for Mobile PCs
2.5V 1.25V Host CLK t t 1.25V
V
HPOFFSET
SS
HPOFFSET
3.3V 1.5V PCI CLK t 1.5V
V
PSKW
SS
3.3V 1.5V PCI CLK
V
SS
Figure 1. Host Clock and PCI CLK Timing
Output Buffer Test Point
Test Load
tHKP
Duty Cycle
tHKH
2.5V Interface
2.0
Clocking 1.25
0.4
tHKL tHrise tHfall
tPKP tPKH
3.3V Clocking Interface (TTL)
2.4 1.5 0.4
tPKL tPrise tPfall
Figure 2. Clock Output Waveforms
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PI6C103 Precision Clock Synthesizer for Mobile PCs
PCB Layout Suggestion
FB1
C6 1 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS Void in Power Plane Via to VDD Plane Via to GND Plane VDD VSS VSS C4 22F VDD C5 C7 VDD FB2 VCC
VCC C1
3 4 5 22F C2 VSS VDD 6 7 8 9 10 11 12 C3 VDD 13 14
Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C2-C6 should be placed as close as possible to their respective VDD.
Recommended capacitor values: C2-C6 ............... 0.1F, ceramic C1, C7 ............ 22F
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PI6C103 Precision Clock Synthesizer for Mobile PCs
Minimum and Maximum Expected Capacitive Loads
Clock CPU Clocks (HCLK ) PCI Clocks (PCLK ) REF, 48MHz M in. Load 10 30 10 M ax. Load 20 30 20 pF Units Note s 1 device load, possible 2 loads Meets PCI 2.1 requirements 1 device load
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of vias of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
21$+!
2 CPUCLK CL 6 PCICLK CL 2 REF CL 1 Device load Meets PCI2.1 Req. 1 Device load
Ordering Information
P/N PI6C103H PI6C103- xxL De s cription 28- pin SSOP Package 28- pin TSSOP Package
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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